1. Field of the Invention
The present invention relates to a logarithmic amplifier circuit and more particularly, to a logarithmic amplifier circuit using bipolar or MOS triple-tail cells. The triple-tail cell contains three bipolar transistors or MOSFETs whose emitters or sources are coupled together and is driven by a tail current.
2. Description of the Prior Art
The logarithmic amplifier circuit is popularly used to logarithmically compress the dynamic range of an input signal for measurement of the received signal strength in radio equipments such as a telemter.
A first conventional logarithmic amplifier circuit is shown in the Japanese Non-Examined-Patent Publication No. 3-127504 published in May 1991, which contains cascaded unit circuits at a plurality of stages. Each of the unit circuits has (a) a first amplifier having a limiting characteristic, i.e., limiter, (b) a second amplifier having no limiting characteristic and a unity gain, i.e., buffer, and (c) a combining circuit for combining the output signals of the first and second amplifiers. Each of the unit circuits further contains (d) an attenuator provided between the output of the first amplifier and the input of the second amplifier. The attenuator attenuates in amplitude the output signal from the corresponding first amplifier so that the attenuated signal causes no saturation in the combining circuit.
With the first conventional logarithmic amplifier circuit disclosed in the Japanese Non-Examined-Patent Publication No. 3-127504, the polygonal line approximation is used to obtain the logarithmic transfer characteristics. Specifically, since the initial input signal is successively amplified in the cascaded first amplifiers or limiters, the earliest output signal saturation occurs in the first amplifier at the last stage, and the subsequent output signal saturations successively occur in the remaining first amplifiers toward the first stage.
Therefore, the number of the stages of the unit circuits is required to be sufficiently large in order to restrict the approximation error to the true logarithmic transfer characteristics in rectification. This means that no logarithmic amplifier circuit having excellent accuracy can be obtained unless the circuit scale is sufficiently large.
A second conventional logarithmic amplifier circuit is shown in the Japanese Non-Examined-Patent Publication No. 2-141012 published in May 1990, which contains a voltage adder amplifier having input ends. The input ends provide different gains to corresponding applied signals. Switching diodes are connected to the input ends, respectively. An input signal is selectively applied to one of the input ends through a corresponding one of the diodes according to the voltage level of the input signal.
With the second conventional logarithmic amplifier circuit disclosed in the Japanese Non-Examined-Patent Publication No. 2-141012, since the polygonal line approximation is used to obtain the logarithmic transfer characteristics, the same problem as that of the circuit of the Publication No. 3-127504 occurs.
A third conventional logarithmic amplifier circuit is shown in the Japanese Non-Examined-Patent Publication No. 62-100010 published in May 1987. This circuit contains (a) cascaded RF amplifiers, (b) detector or rectifier circuits connected to the corresponding amplifiers and detecting the output signals from the corresponding amplifiers, (c) video limiter circuits connected to the corresponding detector circuits and limiting the amplitudes of the output signals from the corresponding detectors, (d) an adder circuit adding the detected output currents from the detectors, and (e) a common-base bipolar transistor the emitter of which is applied with the output current from the adder.
With the third conventional logarithmic amplifier circuit disclosed in the Japanese Non-Examined-Patent Publication No. 62-100010, since the detector or rectifier circuits each having the similar characteristics to the logarithmic ones are used, an error caused by the polygonal line approximation can be reduced. However, it is difficult to arbitrarily adjust the basic logarithmic transfer characteristics such as logarithmic accuracy, slopes of transfer curves and a dynamic range.
A fourth conventional logarithmic amplifier circuit, which was invented by the inventor, Kimura, is shown in the Japanese Examined-Patent Publication No. 3-228412 published in October 1991. This circuit contains (a) cascaded differential amplifiers at n stages where n&gt;1, (b) a first rectifier connected to the input end of the amplifier at the first stage, (c) n second rectifiers connected to the output ends of the amplifiers at the second to n-th stages, and (d) an adder for adding the output signals from the first rectifier and from all the second rectifiers.
Each of the rectifiers has an unbalanced emitter-coupled differential pair of bipolar transistors and an unbalanced source-coupled differential pair of metal-oxide-semiconductor field-effect transistors (MOSFETs). The bipolar and MOS differential pairs have an output end pair, and the output currents outputted from the output end pair are subtracted by a subtracter. The adder adds the outputs from all the subtracters.
With the fourth conventional logarithmic amplifier circuit disclosed in the Japanese Examined-Patent Publication No. 3-228412, similar to that of the Japanese Non-Examined-Patent Publication No. 62-100010, an error caused by the polygonal line approximation can be reduced. However, it is difficult to arbitrarily adjust the basic logarithmic transfer characteristics because each of the rectifiers employs the unbalanced differential pairs.
Especially, since the unbalanced differential pairs are used, it is impossible to change the logarithmic characteristics after the logarithmic amplifier circuit is realized on a semiconductor integrated circuit device.
Also, the differential pairs each requires a driving current source. The differential pairs have large parasitic capacitances due to the connection states of the collectors or drains at output ends of the triple-tail cell. Accordingly, a necessary driving current tends to become large in order to expand the frequency characteristic of the logarithmic amplifier circuit, which results in the difficulty of power consumption reduction.
A fifth conventional logarithmic amplifier circuit, which was invented by the inventor, Kimura, is shown in the Japanese Examined-Patent Publication No. 6-22304 published in March 1994. This publication is equivalent to the Japanese Non-Examined-Patent Publication No. 62-293807 published in December 1987, and corresponds to the U.S. Pat. No. 4,794,342 patented on Dec. 27, 1988.
This circuit is an intermediate-frequency (IF) logarithmic amplifier circuit containing (a) n cascaded differential IF amplifiers where n&gt;1, (b) a first differential pair applied with an initial input voltage and provided at a first stage, (c) n second differential pairs applied with corresponding output voltages from the n differential IF amplifiers and provided at second to n-th stages, and (d) an adder for adding the output voltages from the first differential pairs and from all the second differential pairs.
The first differential pair has two unbalanced emitter-coupled pairs of bipolar transistors. Each of the second differential pairs also has two unbalanced emitter-coupled pairs of bipolar transistors.
With the fifth conventional logarithmic amplifier circuit disclosed in the Japanese Examined-Patent Publication No. 6-22304, the same problem as that in the fourth conventional circuit occurs.
A sixth example of conventional logarithmic amplifier circuits, which was invented by the inventor, Kimura, is shown in the Japanese Examined-Patent Publication No. 6-56940 published in July 1994. This publication is equivalent to the Japanese Non-Examined-Patent Publication No. 62-292010 published in December 1987.
This circuit contains (a) n cascaded MOS differential amplifiers where n&gt;1, (b) a first MOS differential pair applied with an initial input voltage and provided at a first stage, (c) n second MOS differential pairs applied with corresponding output voltages from the n differential amplifiers and provided at second to n-th stages, and (d) an adder for adding the output voltages from the first differential pairs and from all the second differential pairs.
The first differential pair has two unbalanced source-coupled pairs of MOSFETs. Each of the second differential pairs also has two unbalanced source-coupled pairs of MOSFETs.
With the sixth conventional logarithmic amplifier circuit disclosed in the Japanese Examined-Patent Publication No. 6-56940, the same problem as that in the fourth conventional circuit occurs.
A seventh example of conventional logarithmic amplifier circuit, which was invented by the inventor, Kimura, is shown in the Japanese Non-Examined Patent Publication No. 4-165805 published in June 1992. This publication corresponds to the U.S. Pat. No. 5,319,264 patented on Jun. 7, 1994.
This circuit contains (a) n cascaded differential amplifiers where n&gt;1, (b) a first full-wave rectifier for producing an output current having a square-law characteristic and provided at a first stage, (c) n second full-wave rectifiers for producing output currents each having a square-law characteristic and provided at second to n-th stages, and (d) an adder for adding the output currents from the first rectifier and from all the second rectifiers.
The first rectifier has two unbalanced source-coupled pairs of MOSFETs. Each of the second rectifiers also has two unbalanced source-coupled pairs of MOSFETs.
With the seventh conventional logarithmic amplifier circuit disclosed in the Japanese Non-Examined Patent Publication No. 4-165805, the same problems as that of the Japanese Non-Examined-Patent Publication No. 62-100010 occurs.
Additionally, bipolar and MOS pseudologarithmic rectifiers applicable to the logarithmic amplifier circuit is disclosed in IEEE TRANSACTIONS ON CIRCUIT AND SYSTEMS, FUNDAMENTAL THEORY AND APPLICATIONS, Vol. 39, No. 9, September 1992, which was written by the inventor, Kimura. Each of the rectifiers contains two unbalanced, emitter or source-coupled differential pairs of bipolar transistors or MOSFETs.